FAQ - Latches & Registers

Q1: How does an RS latch built with NAND gates work?

Q2: What are critical times for registers?

Q3: What is the difference between Qo and Zo?

Q4: How do I implement a transparent latch?

Q1:
I understand how a latch works using NOR gates but not using NAND
gates like this one uses. How do you know what the different states
are. especially since some of them will depend on the previous state
and some won't?

A NAND gate RS latch operates similarly to a NOR gate RS latch; except
that the R and S signal are active low. The hold state is when R and S
are high.

Q2:
In Fall 2000 final exam problem 3C, when would the output copy
exactly what the input is? Is it when the WE is high at the point
that phi 1 drops, and WE continues to stay high?

For registers, there are only two significant moments in a timing
diagram. When phi1 falls, if WE is high, IN is sampled (captured) for
the next cycle. When phi2 rises, the new sampled value becomes
available on Out (if RE is high).

Q3:
What is the difference between Q not and Z not?

Qo represents the last written state in a storage device. Zo
represents a floating state (driven by an open pass gate).

Q4:
Looking through the practice problems there are many different
ways to implement latches. How are we supposed to figure out which
implementation will work? Is tracing through the latch to make sure
its transparent the only way? Is there a technique to implementing
latches using certain components? The method i use now is really
trivial and I think it has to be wrong. Any help you can provide is
appreciated.

To first approximation, there are three ways to create a transparent
latch.

(1) Use cross-coupled NOR gates to create an RS latch and then
generate R and S signals using Input and Enable

(2) Use cross-coupled NAND gates to create an RS latch and then
generate -R and -S signals using Input and Enable

(3) Use two inverters and a 2 to 1 MUX (most often implemented using
pass gates).

Try to understand these three methods. Please try to ignore the mixed
logic notation in the latch study problems; I'm trying to remove that
because it just causes confusion with cross-coupled outputs.