FAQ - Memory

Q1: How are memory cells organized on a memory chip?

Q2: What decoder will I need in a memory system?

Q3: In a PC, what voltages constitute "high" and "low"?

Q4: In memory, what is parity used for?

Q1:
In Fall 2000 exam three problem 1 B, I don't understand the questions
and answers. I was hoping you could explain it to me.

If the memory cell and the array of memory cells are square, the
number memory cells in a column or row is the square root of the total
number of cells. Powers of two make this computation easy. The words
per column is computer from the word size and column size. The column
decoder is derived from the number of columns. The number of muxes is
equal to the word size since each bit of the word must be selected
from the words within a column by its own mux. The mux size (not asked
for on this problem is the number of words per column to 1.

Q2:
In Fall 2000 exam three problem 1B, consider an 8 Gbyte memory system
organized as 1 billion addresses of 64 bit words. My solution: the
number of banks for a memory system = 1B/32M = 1M/32 ~ 32K hence we
need a 50 to 32K decoder and 8x32K DRAM chips. The given solution is
not the same. Does it have to do anything with the 8 GByte memory
system?

1B/32M = 32, not 32K; remember that billion is the same as giga (G); a
trillion is the same as tera (T). The 8 Gbyte parameter is not
important here.

Q3:
I noticed that every power supply, when you're connecting it to the
motherboard inside your PC, has two voltage lines coming out of it. In
most current processors, the two lines of voltage are 5V and 3.3V. I
wanted to ask you if these actually corresponded to the "high" and
"low" voltage levels we discussed in class.

No. In current PCs, "low" is the zero voltage (ground) level. 5V and
3.3V are provided for compatibility with old chips and peripherals
(5V), and newer chips (3.3V). In fact, most processors are operating
at voltages lower than 3.3V (2.5V to 1.8V) and sub-1V supply voltages
are right around the corner. Lower supply voltages reduces the amount
of power dissipated during processor operation.

Q4:
I have a question on something you mentioned in class on Friday,
when you discussed parity relating to RAM. I kind of got lost when you
discussed that aspect of memory chips, so I was wondering if you could
just explain again how RAM "uses" parity in the sense of how we
discussed it, and how error correction technology works.

In the "old days", each eight bit unit of memory (called a BYTE) had
an extra parity bit added to form a nine bit value. The extra bit is
set to 1 or 0 based on the values of the eight data bits such that the
total number of ones is always an odd number. Then the nine bit value
is stored in memory. When the nine bit value is retrieved from memory,
the parity of the bits is again tested (using a nine input XOR gate).
If one bit is corrupted (inverted) while the value is being stored,
the parity for the nine bit value is changed and a error signal is
generated.

Today, more sophisticated error detection techniques are used in large
memory computers (servers, high reliability computers, etc.) that can
detect multiple corrupted bits, and in many cases correct the
error rather than just detect it. But these technique requires
significant memory overhead (extra bits) and are not widely used on
most PCs. If the software (OS, applications, etc.) crash the system
every few hours, why should we worry about a hardware (memory) error
once every couple of years. In fact, we can define the point where
hardware problems cause an effect greater than normal OS buggyness as
the "Microsoft Threshold(tm)".

ENGINEER: "Hey boss, we forgot to solder the chips onto the
motherboard in the last 50 computers through the production line!"

MANAGER: "Don't worry; they're within the Microsoft Threshold(tm)."