Sequential Logic Timing

Up to this point, the discussion has treated the state machine as an abstract behavioral model, but our ultimate goal as digital hardware engineers is to create electronic hardware that implements that behavior. Because real electronic devices take a finite amount of time to respond to changes on signals, and because with sequential logic, the correct behavior depends on values changing in predictable, synchronized ways, the timing of sequential logic circuits is critically important.

Flip-Flop Clock-to-Q Propagation Delay

A rising edge on the clock causes a flip-flop's output to change. Just like with every digital device, a change on an input cannot cause an instantaneous change on an output. That fact is encapsulated in the concept of propagation delay, which has already been discussed, and is the same with flip-flops.

Of note though is that a change on a flip-flop’s D input cannot cause a change on Q. Only a clock edge can cause Q to change.

Setup and Hold Times

For a flip-flop to correctly capture the value on its input (i.e. latch D onto Q), the value on the D input must be stable around the moment of the clock edge. This requirement is defined by two parameters: setup time and hold time.

Setup Time (Tsu) is the amount of time before the clock edge that the input D must be stable. In other words, D must not be changing right before the clock edge, so that the flip-flop has a valid logic level to sample.
Hold Time (Th) is the amount of time after the clock edge that D must remain stable. This ensures that the sampled value does not get corrupted while the value is being latched.

If either requirement is violated, the flip-flop may have unpredictable behavior.

Note that neither Tsu nor Th are things that happen (like propagation delay is). Setup and hold times are requirements. Requirements that you must ensure are met in order for the circuit to behave correctly.

What Happens After a Clock Edge

In a sequential logic circuit, a clock edge changes the state. A subsequent clock edge would also change the state, but after the first clock edge, several things need to happen before the next clock edge occurs:

Each flip-flop latches in the value on its D input. After the flip-flop's propagation delay, Q outputs change to reflect the newly captured values. Note that because the flip-flops are clocked together, this happens concurrently for all flip-flops.
The updated Q outputs feed into the surrounding combinational logic, which causes changes throughout that logic. The propagation of those changes through the circuit can be modeled as previously discussed (see the "Circuit Timing" topic).
Eventually, the next-state values (at the D inputs of the flip-flops) update. How long that takes depends on what gates are in the propagation paths.

At that point, the values that will become the next state have updated and are ready to be clocked in by another clock edge. However, at that point, the D inputs of the flip-flops have just changed, so if a clock edge occurred at that moment, it would violate the setup and/or hold time of the flip-flops. Thus, some additional time must pass before it would be safe to clock the flip-flops. Analyzing the situation, it is clear that with the clock edge happening after the D inputs changed, the timing requirement in danger of being violated is the setup time, so waiting for the setup time to expire (after the last change to the D inputs) will ensure that the correct value gets latched in when that second clock edge occurs.

The clock period (the amount of time between successive clock edges) must be long enough to allow all these events to complete before the next clock edge arrives.

Input Timing Constraints

State machine inputs often come from external sources — such as other chips, sensors, or systems with independent clocks. These signals may not be synchronized to the system’s clock and could change at arbitrary times relative to the clock edge. If an asynchronous signal changes too close to a clock edge, it may violate setup or hold times for the flip-flop that samples it, risking unpredictable behavior.

Exactly when around a clock edge the circuit inputs must not change depends on what logic is between those inputs and the flip-flops' D inputs. The analysis of these contraints is easiest to perform by assuming that a clock edge occurs at a given time (such as t=0), and investigating at what times changes on the circuit inputs would cause timing requirement violations at that clock edge.